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1 video ics secam chroma signal processor for vhs vcrs ba7207as / ba7207ak the ba7207as and ba7207ak are lsi components that incorporate the contain circuitry required for secam chro- ma signal processing. the ics have both recording and playback systems and each includes a bell filter, a band- pass filter, a limiter amplifier, a multiply-by-four circuit, a divide-by-four circuit, and a sync-gate circuit. applications secam and vhs format video cassette recorders and camcorders features 1) all filters required for secam chroma signal pro- cessing are provided. 2) built-in chroma killer circuit. 3) built-in switch circuit for selecting pal chroma or secam chroma for the pb / rec system output. absolute maximum ratings (ta = 25?) recommended operating conditions (ta = 25?) parameter symbol limits unit power supply voltage power dissipation storage temperature v cc 7v ba7207as ba7207ak ba7207as ba7207ak mw pd topr c tstg c 1400 ( sdip32 ) * 1 ? 25 ~ + 75 850 ( qfp44 ) * 2 ? 25 ~ + 65 ? 55 ~ + 125 * 1 reduced by 14mw for each increase in ta of 1 c over 25 c . * 2 when mounted on a 70mm 70mm, t = 1.6mm glass epoxy board, reduced by 8.5w for each increase in ta of 1 c over 25 c. operating temperature parameter symbol min. typ. max. unit operating power supply voltage v cc 4.5 5.0 5.5 v
2 video ics ba7207as / ba7207ak block diagram 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 3 4 5 6 7 8 9 10111213141516 12 vreg 2 2 2.2mhz bpf pal scm r r p p p r r p p p r r 4.3mhz bpf a 4.3mhz bpf - b pb sync gate 1.1mhz bpf mode contorol rec sync gate sync gate timing generator bell det vco scm pal 4 eq lim lim syncin div palpin sgc sgadj pbout vco det scmpin gnd ampout gnd1 fadj2 fadj1 mul recin bwl pbin rech cref3 ctl lao v cc lain cref1 abelo cref2 recout trap palrin vreg 4o frequency adjuster ba7207as ( sdip32 ) ba7207ak ( sqfp44 ) pal scm vreg 2 2 4 lim lim v cc cref3 rech pbin n.c. bwl n.c. syncin n.c. div palpin sgc trap palrin vreg n.c. 4o n.c. recin n.c. mul fadj1 fadj2 p p p r p p r r p r r eq det vco scm pal bell frequency adjuster sync gate timing generator 1.1mhz bpf 2.2mhz bpf 4.3mhz bpf? 4.3mhz bpf? pb sync gate rec sync gate r mode control 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 11 10 9 8 7 6 5 4 3 2 1 gnd ampout gnd1 n.c. scmpin n.c. det n.c. vco pbout sgadj abelo cref2 recout n.c. cref1 n.c. lain n.c. vcc lao ctl
3 video ics ba7207as / ba7207ak pin descriptions pin name 1 ( 40 ) recin 2 ( 42 ) mul 3 ( 43 ) fadj1 4 ( 44 ) fadj2 5 ( 1 ) gnd1 6 ( 2 ) ampout 7 ( 3 ) gnd 8 ( 5 ) scmpin 9 ( 7 ) det 10 ( 9 ) vco 11 ( 10 ) pbout 12 ( 11 ) sgadj 13 ( 12 ) sgc pin no. function recording system input. input the rec system chroma signal. pb sync gate output. test pin. outputs the chroma signal after it is multiplied by four and passed through the sync gate. normally connected to v cc to prevent interference. filter fo adjustment pin 1. used to adjust fo for the equalizer, 1.1mhz bpf and 2.2mhz bpf. connect a resistor and variable resistor from this pin to gnd. filter fo adjustment pin 2. used to adjust fo for the bell filter, 4.3mhz bpf-a and 4.3mhz bpf-b. connect a resistor and variable resistor from this pin to gnd. ground. pb system preamplifier output. connect to gnd via a variable resistor to adjust the level, and input to pin 8. ground. pb system output amplifier input. input the level-adjusted pb system secam chroma signal. phase comparator output. connect to gnd via a rc lpf to obtain the error voltage. vco oscillator frequency control pin. the error voltage is input via a resistor. connected to gnd via free-running frequency setting resistor. pb system output. outputs the pb system chroma signal. fine adjustment for the sync gate phase. the voltage from a resistor divider is used for fine adjustment of the gate phase of the sync gate. normally open. sync gate timing output. test pin. outputs the rec sync gate timing. normally open. 14 ( 13 ) palpin 15 ( 14 ) div 16 syncin pal pb system input. input chroma signal for the pal pb system. divide-by-four divider output. test pin. outputs the chroma signal after it has been divided by four. normally connected to v cc to prevent interference. delayed sync signal input. input the synchronously-separated composite 17 ( 18 ) bwl 18 ( 20 ) pbin 19 ( 21 ) rech 20 ( 22 ) cref3 21 ( 23 ) ctl 22 ( 24 ) lao 23 ( 25 ) 24 ( 27 ) lain 25 ( 29 ) cref1 26 ( 31 ) abelo 27 ( 32 ) cref2 ba7207ak pin numbers are given in brackets. pin name pin no. function v cc chroma killer mode setting . "l" sets the ic in chroma killer mode. pb system input . input chroma signal for the pb system. rec / pb mode switch. set to open or "h" for rec mode, "l" for pb mode. bias terminal for the limiter amplifier before 2. connect to gnd via a capacitor. secam / pal output switch. selects the signal output for the rec / pb terminal. set to open or "h" for secam output mode, "l" for pal mode. limiter amplifier output. test pin. outputs the amplitude-limited chroma signal. normally connected to v cc to prevent interference. power supply. limiter amplifier input. input the de-emphasised chroma signal. limiter amplifier bias pin 1. connect to gnd via a capacitor. rec bell output. when in rec mode, de-emphasised chroma signal is output via rec bell. when in pb mode, the pb system chroma signal is output after being multiplied by four. limiter amplifier bias pin 2. connect to gnd via a capacitor. 28 ( 33 ) recout 29 ( 34 ) trap 30 ( 35 ) palrin rec system output. rec system chroma signal output. trap connection. connect trap that rejects spurious signal component after 2 multiplication. pal rec system input. pal rec system chroma signal input. 31 ( 36 ) vreg 32 ( 38 ) 40 regulated voltage output. output for the regulated 2.5v reference voltage used for internal biasing. connect to gnd via a bypass capacitor. 4 multiply output. test pin. outputs the chroma signal after it is multiplied by four. normally connected to v cc to prevent interference.
4 video ics ba7207as / ba7207ak input / output circuits recin v cc 40k 40k gnd 1pin (40pin) mul v cc v cc gnd 2pin (42pin) fadj1 v cc v cc gnd gnd 3pin (43pin) fadj2 v cc v cc gnd gnd 4pin (44pin) gnd gnd1 5pin (1pin) ampout v cc v cc 5k gnd 6pin (2pin) gnd gnd 7pin (3pin) scmpin v cc 20k 30k gnd 8pin (5pin) scmpin v cc 20k 30k gnd 9pin (7pin)
5 video ics ba7207as / ba7207ak vco v cc gnd gnd 12k 5k 10pin (9pin) pbout v cc v cc gnd 2.2k 11pin (10pin) sgadj v cc v cc gnd gnd 50k 50k 100k 12pin (11pin) sgc v cc 10k 10k gnd 13pin (12pin) palpin v cc 20k 30k gnd 14pin (13pin) div v cc v cc gnd 15pin (14pin) syncin v cc 15k 35k gnd 16pin bwl v cc 50k gnd 17pin (18pin) pbin v cc 20k 20k gnd 18pin (20pin) rech v cc gnd 50k 19pin (21pin) cref3 gnd v cc 20pin (22pin) ctl v cc 50k gnd 21pin (23pin)
6 video ics ba7207as / ba7207ak lao v cc v cc gnd 22pin (24pin) v cc v cc 23pin (25pin) lain v cc gnd gnd 2k 24pin (27pin) cref1 v cc 30k 2k gnd gnd 25pin (29pin) abelo v cc v cc gnd 1.8k 26pin (31pin) cref2 v cc gnd gnd 2k 30k 27pin (32pin) recout v cc v cc gnd 1.8k 28pin (33pin) trap v cc gnd 560 200 29pin (34pin) palrin v cc 20k 30k gnd 30pin (35pin) vreg v cc 5.3k gnd v cc 3k 3k 31pin (36pin) 4o v cc v cc gnd 32pin (38pin) pin numbers in parentheses are for the ba7207ak.
7 video ics ba7207as / ba7207ak electrical characteristics (unless otherwise noted, ta = 25?, v cc = 5.0v) parameter symbol min. typ. max. unit conditions measurement circuit i rec 39.2 56.0 72.8 ma rec mode fig.1 i pb 46.9 67.0 87.1 ma pb mode v reg 2.38 2.53 2.68 v fig.1 fosc 13.8 15.625 17.4 fig.1 cr h 1.8 khz fig.1 cr l ? 1.8 khz fig.1 lr h 2.2 khz fig.1 lr l ? 2.2 khz fig.1 v rec mv p-p cyan level (cyan frequency) fig.1 hd r4 ? 25 fig.1 hd r3 ? 25 db fig.1 hd r2 ? 25 db fig.1 g rs ? 1 0 1 db fig.1 f rs ? 1 0 1 db fig.1 ct r1 ? 60 db fig.1 ct r2 ? 60 db fig.1 v pb cyan level (cyan frequency) fig.1 hd p3 ? 35 db fig.1 hd p2 ? 35 db fig.1 hd p1 ? 35 db fig.1 g p1 5 6 7 db fig.1 f p1 ? 1 0 1 db fig.1 ct p1 ? 60 db fig.1 g p2 ? 1 0 1 db fig.1 ? 1 0 1 db fig.1 ct p2 ? 60 db v 14 = 0.3v p-p , 4.43mhz fig.1 ct rin ? 40 ? 30 db fig.1 2.5 v fig.1 v l 1.5 v fig.1 f p2 v h pins 14, 17, 19, 21 and 30 (pins 13,18,21,23 and 35) * pins 14, 17, 19, 21 and 30 (pins 13,18,21,23 and 35) * v 1 = 0.5v p-p , 4.286mhz v 14 = 0.3v p-p , 5mhz / 100khz v 8 = 0.3v p-p , 4.3mhz v 8 = 0.3v p-p , 5mhz / 100khz v 8 = 0.3v p-p , 4.3mhz mv p-p v 30 = 0.3v p-p , 627khz v 18 = 25mv p-p , 1.0715mhz v 30 = 0.3v p-p , 5mhz / 100khz v 30 = 0.3v p-p , 627khz v 14 = 0.3v p-p , 4.43mhz fig.1 khz delayed sync input delayed sync input delayed sync input delayed sync input v 1 = 170mv p-p , 4.286mhz v 1 = 170mv p-p , 4.286mhz v 1 = 170mv p-p , 4.286mhz db v 18 = 25mv p-p , 1.0715mhz v 18 = 25mv p-p , 1.0715mhz v 18 = 25mv p-p , 1.0715mhz 187.5 250.0 312.5 202.5 270.0 337.5 [total device] rec mode supply current pb mode supply current regulator voltage [sync-gate block] vco free-running frequency capture range "h" capture range "l" lock range "h" lock range "l" [rec system] recout output amplitude unwanted spectrum rejection 4mhz component 3mhz component 2mhz component output switch voltage gain output switch frequency characteristic output switch crosstalk 1 output switch crosstalk 2 [pb system] pb output amplitude unwanted spectrum rejection 3mhz component 2mhz component 1mhz component output switch voltage gain 1 output switch frequency characteristic 1 output switch crosstalk 1 output switch voltage gain 2 output switch frequency characteristic 2 output switch crosstalk 2 recin crosstalk [control system] high level voltage low level voltage * ba7207ak pin numbers are given in brackets.
8 video ics ba7207as / ba7207ak parameter symbol unit conditions max. min. typ. ? 2.8 0.7 4.2 db fig.1 ? 6.5 ? 3.0 0.5 db fig.1 ? 35.0 ? 26.0 db fig.1 ? 11.3 db fig.1 db fig.1 db fig.1 g rb1 db fig.1 g rb2 db fig.1 g rb3 db fig.1 g pb1 db fig.1 g pb2 db fig.1 g pb3 db fig.1 g re1 db fig.1 g re2 db fig.1 g re3 db fig.1 g pe1 db fig.1 g pe2 ? 5.1 ? 1.6 1.9 db fig.1 g pe3 db fig.1 g f11 g f12 g f13 g f31 g f32 g f33 v 18 = 25mv p-p , 1.0715mhz v 18 = 25mv p-p , 0.5mhz v 18 = 25mv p-p , 3.2145mhz v 1 = 500mv p-p , 4.286mhz v 1 = 500mv p-p , 3.2mhz v 1 = 500mv p-p , 5.5mhz v 1 = 170mv p-p , 4.286mhz v 1 = 170mv p-p , 4.1mhz v 1 = 170mv p-p , 4.5mhz v 1 = 800mv p-p , 4.286mhz v 1 = 800mv p-p , 4.1mhz v 1 = 800mv p-p , 4.5mhz v 18 = 95mv p-p , 1.0715mhz v 18 = 95mv p-p , 1.0mhz v 18 = 25mv p-p , 1.0715mhz v 18 = 25mv p-p , 1.0mhz v 18 = 25mv p-p , 1.2mhz v 18 = 95mv p-p , 1.2mhz ? 16.1 ? 14.0 ? 7.8 ? 12.6 ? 10.5 ? 4.3 ? 9.1 ? 7.0 6.3 0 ? 0.2 ? 3.7 ? 3.5 2.8 ? 7.2 ? 7.0 ? 0.7 ? 20.9 ? 16.2 ? 15.3 ? 17.4 ? 12.7 ? 11.8 ? 13.9 ? 9.2 ? 8.3 ? 4.0 ? 0.5 3.0 11.1 13.7 7.6 10.2 6.7 4.1 2.5 ? 8.9 6.0 ? 5.4 9.5 ? 1.9 [filter block] 1.1mhz bpf characteristic ? 1.1mhz voltage gain 0.5mhz voltage gain 3.2mhz voltage gain 4.3mhz bpf - a characteristic ? 4.3mhz voltage gain 3.2mhz voltage gain 5.5mhz voltage gain rec bell + 4.3mhz bpf - a characteristic ? 4.3mhz voltage gain 4.1mhz voltage gain 4.5mhz voltage gain pb bell + 4.3mhz bpf - a characteristic ? 4.3mhz voltage gain 4.1mhz voltage gain 4.5mhz voltage gain rec eq + 1.1mhz bpf characteristic ? 1.1mhz voltage gain 1.0mhz voltage gain 1.2mhz voltage gain pb eq + 1.1mhz bpf characteristic ? 1.1mhz voltage gain 1.0mhz voltage gain 1.2mhz voltage gain measurement circuit guaranteed design parameters (unless otherwise noted, ta = 25?, v cc = 5.0v, delayed sync input) parameter symbol unit conditions min. typ. max. rec sync-gate phase pb sync-gate phase rec sync-gate amplitude pb sync-gate amplitude t dr 2.4 m s t dp 1.6 m s t wr 4.9 5.2 5.5 m s t wp 6.1 6.4 6.7 m s div (pin 14 / pin 15), rec mode mul (pin 2 / pin 42), pb mode div (pin 15 / pin 14), rec mode mul (pin 2 / pin 42), pb mode the pin numbers in brackets are for the ba7207as and the ba7207ak respectively. 1.3 0.5 3.5 2.7
9 video ics ba7207as / ba7207ak reference design data (unless otherwise noted, ta = 25?, v cc = 5.0v, fo (rec bell) = 4.286mhz, fo (pb eq) = 1.0715mhz) parameter symbol unit conditions min. typ. max. 1.1mhz gain 0.5mhz suppression ratio 3.2mhz suppression ratio groupe delay time 2.2mhz gain 1.1mhz suppression ratio 3.2mhz suppression ratio groupe delay time 4.3mhz gain 3.2mhz suppression ratio 5.5mhz suppression ratio groupe delay time 4.3mhz gain 3.5mhz suppression ratio 5.2mhz suppression ratio groupe delay time 4.3mhz gain 4.1mhz suppression ratio 4.5mhz suppression ratio 4.3mhz gain 4.1mhz gain 4.5mhz gain center frequency ratio 1.1mhz gain 1.0mhz suppression ratio 1.2mhz suppression ratio 1.1mhz gain 1.0mhz gain 1.2mhz gain center frequency ratio g f11 1.0 db g f12 ? 4.0 db g f13 ? 30.0 db 370 420 470 ns g f21 ? 6.0 db g f22 db g f23 ? 25.0 ? 25.0 db d f2 180 230 280 ns g f31 7.0 db g f32 ? 3.0 db g f33 ? 3.0 db d f3 160 210 260 ns g f41 9.0 db g f42 ? 3.0 db g f43 ? 3.0 db d f4 250 300 350 ns g rb1 db g rb2 db g rb3 db g pb1 db g pb2 db g pb3 db ? 101 % g re1 db g re2 db g re3 db g pe1 db g pe2 db g pe3 db df oe ? 101 % df ob 19.5 ? 5.0 ? 5.5 ? 19.5 5.0 5.5 19.5 ? 8.0 ? 11.0 ? 19.5 8.0 11.0 v in = 0.3v p-p , 1.0715mhz v in = 0.3v p-p , 0.5mhz v in = 0.3v p-p , 3.2145mhz v in = 0.3v p-p , 1.0715mhz v in = 0.3v p-p , 2.143mhz v in = 0.3v p-p , 1.0715mhz v in = 0.3v p-p , 3.2145mhz v in = 0.3v p-p , 2.143mhz v in = 0.1v p-p , 4.286mhz v in = 0.1v p-p , 3.2mhz v in = 0.1v p-p , 5.5mhz v in = 0.1v p-p , 4.286mhz v in = 0.1v p-p , 4.286mhz v in = 0.1v p-p , 3.5mhz v in = 0.1v p-p , 5.2mhz v in = 0.1v p-p , 4.286mhz v in = 0.3v p-p , 4.286mhz v in = 0.3v p-p , 4.1mhz v in = 0.3v p-p , 4.5mhz v in = 0.3v p-p , 4.286mhz v in = 0.3v p-p , 4.1mhz v in = 0.3v p-p , 4.5mhz v in = 0.3v p-p , 1.0715mhz v in = 0.3v p-p , 1.0mhz v in = 0.3v p-p , 1.2mhz v in = 0.3v p-p , 1.0715mhz v in = 0.3v p-p , 1.0mhz v in = 0.3v p-p , 1.2mhz df oe = ( f o ( rec ) ? f o ( pb ) ) / f o ( pb ) df ob = ( f o ( pb ) ? f o ( rec ) ) / f o ( rec ) d f1 1.1mhzbpf ? 2.2mhzbpf ? 4.3mhz bpf - a ? 4.3mhz bpf - b ? rec bell ? pb bell ? pb eq ? rec eq ?
10 video ics ba7207as / ba7207ak vreg 2 2 2.2mhz bpf pal scm r r p p p p p r r r r 4.3mhz bpf - a 4.3mhz bpf - b pb sync gate 1.1mhz bpf mode contorol rec sync gate sync gate timing generator bell det vco scm pal 4 eq lim lim v 2.5v 1.5v sgc pbout 1n2 1 1 1 2 12 12 23 2 12 vcc 33k 3.3k 0.01 m 2 sg16 1 sw16 sw15 sw14a osc14 sw14b 100k 10k 4700p 0.01 m 0.47 m 12 m 560p osc8 ampout sw8 470 470 sw2 sw3 sw4 vcc 7.5k 7.5k 8.5k 8.5k 3.9k 2k vr2 2k vr1 0.01 m osc1 frequency adjuster ctl bwl rech a vcc vcc 47 m 0.01 m 0.01 m 0.01 m 0.1 m 0.1 m 0.1 m 0.1 m 47 m 0.1 m 27p recout vcc vreg 12 12 sw30b osc30 sw30a 1 1 1 2 2 2 n n n sw21 sw19 sw18 osc18 i23 100p v fig. 1 ba7207as (sdip32) 32 31 30 28 27 26 25 24 23 22 21 20 19 18 17 29 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 4 + + measurement circuits
11 video ics ba7207as / ba7207ak a ~ ~ ~ ~ ~ 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 + + pal 0.1 m 0.1 m 0.1 m v cc v cc i23 47 m 0.1 m 0.01 m 100p sg16 sw16 2 1 osc18 sw18 2 1 osc14 v cc sw14a 2 1 sw15 rec sg out sgc pb out amp out pb sg out 2 3.3k 1 0.01 m 0.47 m 0.01 m 12 m 0.01 m 0.1 m 0.01 m 47 m 27p osc30 v cc vreg sw30a sw30b rec out 1n 2 12 osc1 560p 470 470 sw8 osc8 100k 33k 10k 123 4700p 0.01 m scm vreg 2 2 4 lim lim v cc p p p r p p r r p r r eq det vco scm pal bell frequency adjuster sync gate timing generator 1.1mhz bpf 2.2mhz bpf 4.3mhz bpf a 4.3mhz bpf b pb sync gate rec sync gate r mode control sw3 sw4 2k 2k 7.5k 7.5k 8.5k 3.9k 8.5k vr1 vr2 12 12 sw2 12 v cc sw21 1n 2 sw19 1n 2 sw4b 1.5v 2.5v 1n 2 fig. 2 ba7207ak (qfp44)
12 video ics ba7207as / ba7207ak circuit operation (1) recording system (rec) the input to rec in is passed through the 4.3mhz bpf-a to remove unwanted frequency components, and is flat- tened by rec bell which has an anti-bell characteristic. the flattened signal is wave-shaped by the limiter amplifer, and processed by the divide-by-four and sync gate circuits. finally, unwanted frequency components are removed by the 1.1mhz bpf and the rec eq prepares the signal for recording playback and the signal is output on rec out. refer to fig. 3. 1 26 24 ( ) ( ) ( ) ( ) 28 4.3mhz bpf - a rec bell limamp 1.1mhz bpf ? 4 rec sync gate rec eq amp recout ba7207as (ba7207ak) 100pf composite video signal fig. 3 33 27 31 40 (2) playback system (pb) the input to pb in is passed through the 1.1mhz bpf to remove unwanted frequency components, and is flattened by the pb eq circuit. the amplitude of the flattened signal fixed by the 1st-stage limiter amplifier, and the frequency is multiplied by four by the multiplier circuit. unwanted frequency components generated by the multiplier circuit are removed by the 2.2mhz bpf and 4.3mhz bpf-a. the signal is wave-shaped by the limiter amplifier, and has gate applied to it by the sync gate circuit then is passed through the 4.3mhz bpf-b to remove unwanted frequency com- ponents. the pb bell circuit restores the original bell characteristic and the signal is output on pb out. refer to fig. 4. 18 1.1mhz bpf pb eq lpf limamp 2.2mhz bpf 4.3mhz bpf - a 2 2 amp ba7207as (ba7207ak) rf chroma signal 24 26 6 8 11 pb sync gate amp amp pbout limamp 4.3mhz bpf - b pb bell trap fc 6 2.2mhz fig. 4 2 5 10 31 27 20 ( ) ( ) ( ) ( ) ( ) ( ) (3) sync gate timing circuit rec and pb sync gate operation is as follows. the gate closes closes in synchronous with the sync in input pulse during the synchronous signal pulse (sync) horizontal scan interval (64 m s period). during vertical retrace (32 m s period), the input pulse period becomes shorter than the horizontal scan interval. this is detected by the built- in vertical synchronous detector circuit which closes the gate. refer to fig. 5. horizontal scan interval vertical retrace interval 4 m s 64 m s 32 m s syncin rec / pbout fig. 5
13 video ics ba7207as / ba7207ak application examples ba7207as (sdip32) to cancel the temperature characteristic of the id, the resistors marked with asterisks should be of the metal film, and have a temperature coefficient 100ppm / c. d : test pin. connect to v cc if unused. the 100pf capacitor connected to pin 16 is intended to reduce temperature disper of the gate phase.it should have a static capacitance tolerance of 10% or ic and a temperature coefficient of 30ppm / c ( ?55 c to + 125 c) a (cg). * vreg 2 2 2.2mhz bpf pal scm r r p p p p p r r r r 4.3mhz bpf - a 4.3mhz bpf - b pb sync gate 1.1mhz bpf mode contorol rec sync gate sync gate timing generator bell det vco scm pal 4 eq lim lim 33k 0.01 0.01 100k 10k 4700p 0.01 0.47 7.5k 7.5k frequency adjuster d 47 0.01 0.01 0.01 0.01 0.1 0.1 0.1 0.01 47 0.1 m 27p d 100 lpf pal rec c. rec c out v cc scm / pal rec / pb pbin b / w sync in palpb c pb c out recin d 100p eq fo adj bell fo adj pbout level * * * * * vr1 vr2 vr3 2kvr 2 d 1k 12 560p 100p fig. 6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 3 4 5 6 7 8 9 10 11 12 13 14 15 16 12 +
14 video ics ba7207as / ba7207ak fig. 7 * * * * * 33 32 31 29 30 28 27 25 24 23 22 21 20 18 16 13 12 15 17 19 34 35 36 38 40 42 43 44 41 39 37 26 1 2 3 5 4 6 10 11 ba7207ak (qfp44) pal 0.1 m 0.01 m 0.01 m 0.1 m 0.01 m 100 m 47 m 0.01 m 0.01 m 0.1 m lpf 100p d d d 0.47 m 0.01 m 0.01 m 12 m 580p 0.1 m 1k vr3 vr2 100k 33k 10k 4700p 0.01 m scm vreg 2 2 4 lim lim v cc p p p r p p r r p r r eq det vco scm pal bell frequency adjuster sync gate timing generator 1.1mhz bpf 2.2mhz bpf 4.3mhz bpf a 4.3mhz bpf b pb sync gate rec sync gate r mode control 2k bell of adj pbout level eq of adj 7.5k vr vr1 2k 7.5k vr 100p 47 m 27p pal rec c. rec c out. v cc scm/pal rec/pb pbin b/w sync in palpb c. pb c out recin d + + to cancel the temperature characteristic of the id, the resistors marked with asterisks should be of the metal film, and have a temperature coefficient 100ppm / c. d : test pin. connect to v cc if unused. the 100pf capacitor connected to pin 16 is intended to reduce temperature disper of the gate phase.it should have a static capacitance tolerance of 10% or ic and a temperature coefficient of 30ppm / c ( ?55 c to + 125 c) a (cg). * 14 7 9 8 control pin logic pin low high ( open ) rec / pb setting switch output select switch chroma killer switch rech ( 19pin / 21pin ) pb rec ctl ( 21pin / 23pin ) pal secam bwl ( 17pin / 18pin ) ( ba7207as / ba7207ak ) chroma killer normal
15 video ics ba7207as / ba7207ak operation notes (1) equalizer fo adjustment set to pb mode and input a 25mv p-p , 1.0715mhz sine wave to pbin. adjust the variable resistor connected between fadj1 and gnd to maximize the rec out output. this adjustment also adjusts the 1.1mhz and 2.2mhz band-pass filters. the value of the variable resistor must be at least 2k w . if it is less than this, adjustment may not be possible. (2) bell filter fo adjustment set to rec mode and input a 170mv p-p , 4.286mhz sine wave to recin. adjust the variable resistor con- nected between fadj2 and gnd to maximize the amp out output. this adjustment also adjusts the 4.3mhz and 4.3mhz a and b band-pass filters. the value of the variable resistor must be at least 2k w . if it is less than this, adjustment may not be possible. (3) test pins the mul, div, lao and 4xo pins are test terminals. by connecting these pins to gnd via a 3.6k w resistor, it is possible to monitor there waveforms. when unused, connect these pins to v cc to prevent interfer- ence. (4) rec / pb input levels the frequency characteristics of the built-in filters can change. for this reason use the following input signal levels: recin: 540mv p-p + / ?6db (cyan level) pbin: 75mv p-p + / ?6db (cyan level) (5) capacitor connected to vreg use a ceramic with a static capacitance of 0.1 m f. the filter may not operate correctly with other capacitance values. (6) pbin input if there is a chroma component imposed on the fm brightness signal, use a low-pass filter (with an fc of about 2.2mhz) to remove the fm brightness signal component, and ensure that only the chroma compo- nent is input to pbin. (7) recin input in the case of composite video input, connect a 100pf capacitor to ensure that only the chroma component is input to recin. (8) sync-gate phase adjustment perform fine adjustment of the sync-gate phase by applying a voltage to the sgadj terminal, or using a resistor divider connected between v cc and gnd. the adjustment sensitivity is shown in fig. 6. sgadj pin voltage when open: v sgadj = 2.5v input impedance z = 125k w 1.5 2.5 3.5 + 3.2 0 ?3.2 0.32 m s / 0.1v sgadj pin apply voltage: v sgadj (v) gate phase adjustment: t dr ( m s) fig. 8 sync-gate phase
16 video ics ba7207as / ba7207ak rec / pb eq frequency: fo (mhz) fadj1 resistance value: r adj1 (k w ) 7.5 8.0 8.5 9.0 9.5 1.3 1.2 1.1 1.0 0.9 fig. 9 rec / pb eq f o frequency adjustment range electrical characteristic curves 6pin rec bell frequency: fo (mhz) 1pin rec in level: v irec (mv p-p ) fo conditions v cc = 5.0v fo = 4.286mhz v = 170mv p-p 0 4.15 4.20 4.25 4.30 4.35 4.40 100 200 300 400 500 fig. 11 rec / bell f o frequency variation rec / pb bell frequency: fo (mhz) fadj2 resistance value: r adj2 (k w ) 7.5 8.0 8.5 9.0 9.5 5.5 5.0 4.5 4.0 3.5 fig. 10 rec / pb bell f o frequency adjustment range 28pin pb eq frequency: fo (mhz) 18pin pb in level: v ipb (mv p-p ) fo conditions v cc = 5.0v fo = 1.0715mhz v = 25mv p-p 1.04 1.05 1.06 1.07 1.08 1.09 0 20 40 60 80 100 fig. 12 pb eq f o frequency variation characteristics pb out level: v opb (dbm) frequency: f (mhz) 2mhz component 1mhz component 3mhz component 6mhz component 8mhz component 7mhz component 5mhz component fundamental frequency component pb in f = 1.0715mhz v = 25mv p-p 02 4 6 8 10 13 57 9 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 fig. 14 pb out spurious characteristics rec out level: v orec (dbm) frequency: f (mhz) fundamental frequency component 2mhz component 3mhz component 4mhz component recin f = 4.286mhz v = 170mv p-p ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0 1.0 2.0 3.0 4.0 5.0 fig. 13 rec out spurious characteristics
17 video ics ba7207as / ba7207ak sdip32 ba7207as ba7207ak 4.7 0.3 0.51min. 8.4 0.3 3.2 0.2 32 116 17 0.5 0.1 0.3 0.1 28.0 0.3 0 ~ 15 10.16 1.778 qfp44 33 23 22 12 1 34 44 10.0 0.2 14.0 0.3 0.35 0.1 10.0 0.2 14.0 0.3 1.2 0.05 2.15 0.1 0.15 0.1 0.8 11 0.15 external dimensions (units: mm)

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